Modern computing devices incorporate electronic processing units which execute stored instructions upon discrete elements of data. In the most common embodiment of such a device, Read Only Memory (ROM) stores a fixed instruction set which, in essence, tells the computing device how to be a computing device. Using instructions stored in ROM, the computing device retrieves further instructions from Random Access Memory (RAM) and processes them with a Central Processing Unit (CPU.) It should be noted that due to network processing and “virtualization,” any or all of the three computing device elements may or may not be in physical proximity to a given user of the computing device or to any of the other two computing device elements.
A drawback of this architecture is that CPUs work on “clock cycles,” and can only execute one instruction on one set of discrete data elements per individual processing unit per clock cycle. Typically this architecture uses single-instruction single-data processing, where a single operation is performed on one or two data items per clock cycle. The two approaches to increasing overall computing speed in this architecture are: 1) To increase the number of processors, allowing more instructions to be executed in total; and/or 2) to increase the number of clock cycles per second that the CPU can execute. To illustrate the progress of the art, two examples are informative:                1) The Motorola® 6800, one of the first modern general-purpose CPUs, had the equivalent of 4,100 transistors (processors) operating at a speed of 1 MHz, or one million clock cycles per second, when introduced in 1974.        2) The Intel® Core i7, a recent-generation general-purpose CPU, had the equivalent of up to 1.9 billion transistors (processors) operating at a speed of up to 3.1 GHz, or 3.1 billion clock cycles per second, when introduced in 2015.        
Increasing the number of processors in a CPU introduces a vast number of problems, including but not limited to size limitations, power consumption and heat dispersal, threading complexity, higher manufacturing error rates, and even quantum-mechanical limits arising in relation to the density of circuits in the processor. A combination storage and processing device that could increase the overall computing speed of a computing device without increasing the number of processors in the CPU, or increasing the density of the processors on the CPU, would be a useful invention.
In addition, as the number of processing units increases, the amount of information which must be moved from RAM to the CPU so it can be acted upon 5 increases. This information is moved through a CPU/RAM data bus. This is one of the major limits to overall computing speed, since data must move through the CPU/RAM data bus from the RAM to the CPU, and often back again after processing, to perform most computing tasks. A combination storage and processing device that could reduce the amount of information moving through the CPU/RAM data bus would be a useful invention.
The present invention addresses these concerns.